URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] - Rev 17

Rev 17, 2001-09-17 11:59:26 GMT
Author: rherveille
Log message:
Major rework.
Included generic memory models.
Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)

Path
/trunk/rtl/verilog/generic_dpram.v
/trunk/rtl/verilog/generic_spram.v
/trunk/rtl/verilog/ro_cnt.v
/trunk/rtl/verilog/ud_cnt.v
/trunk/rtl/verilog/vga_colproc.v
/trunk/rtl/verilog/vga_csm_pb.v
/trunk/rtl/verilog/vga_fifo.v
/trunk/rtl/verilog/vga_fifo_dc.v
/trunk/rtl/verilog/vga_pgen.v
/trunk/rtl/verilog/vga_tgen.v
/trunk/rtl/verilog/vga_top.v
/trunk/rtl/verilog/vga_vga_and_clut_top.v
/trunk/rtl/verilog/vga_vtim.v
/trunk/rtl/verilog/vga_wb_master.v
/trunk/rtl/verilog/vga_wb_slave.v