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  • Rev 37, 2016-03-14 21:43:20 GMT
  • Author: dgisselq
  • Log message:
    These fixes were necessary to get the SDRAM into a working simulation
    capability. It is finally what it was supposed to be: cycle accurate. Sadly,
    to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
    a problem with external input clocking in Verilator. This fixes it--but its
    a Verilator only change--to rtl/wbsdram.v that is.)

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