Subversion Repositories a-z80

Last modification

• Rev 13, 2016-12-09 07:38:06 GMT
• Author: gdevic

• Log message:

  Full support for nWAIT during M1 and memory cycles
  This set of changes fixes issues with nWAIT signal
  Updated reg control, resets, ir modules to handle delay
  This correctly delays clearing of IR if the nWAIT was asserted at
  the very first M1 cycle
  Simplify decode_state to use discrete write enable for CB/ED flags
  Gate CB/ED write with hold_clk_wait to enable nWAIT delay
  genfuse add code to test nWAIT insertion at M1
  Add host wait state circuitry from Zilog manual (wait_state.*)
  Add wait test code to basic fpga/modelsim models
  Select from 3 options to test wait states:
  - no wait state inserted (nWAIT=1)
  - insert a wait state to every M1 cycle
  - insert a wait state to each memory access cycle
  zxspectrum: Add custom NMI handler and a function to enter game pokes after pressing the NMI button
  zxspectrum: Corrected bits 7,5 when reading ULA port 254
  zxspectrum: Fix the shift key repeat bug
  When using additional keys (<,>,?,...) and shift was released before
  a symbol, it would repeat. This change fixes that by correctly resetting
  keyboard mask state bitfields.
  Added new data pins module for Lattice toolset
  It has been reported that "data_pins.v" does not compile on Lattice
  toolset and this variation of the code has been proposed and verified
  by a user.
  Fixed M1 during reset
  Memory_ifc module set M1 to inactive (high) during nRESET
  Exported wait_m1 signal from that module as a testpoint