URL https://opencores.org/ocsvn/ata/ata/trunk

Subversion Repositories ata

[/] [ata/] [trunk/] [bench/] [verilog/] - Rev 16

Rev 16, 2001-08-16 10:01:05 GMT
Author: rudi
Log message:
- Added Test Bench
- Added Synthesis scripts for Design Compiler
- Fixed minor bug in atahost_top

Path
/trunk/bench
/trunk/bench/verilog
/trunk/bench/verilog/ata_device.v
/trunk/bench/verilog/tests.v
/trunk/bench/verilog/test_bench_top.v
/trunk/bench/verilog/wb_mast_model.v
/trunk/bench/verilog/wb_model_defines.v
/trunk/bench/verilog/wb_slv_model.v
/trunk/rtl/verilog/ocidec-1/atahost_top.v
/trunk/sim
/trunk/sim/rtl_sim
/trunk/sim/rtl_sim/bin
/trunk/sim/rtl_sim/bin/Makefile
/trunk/syn
/trunk/syn/bin
/trunk/syn/bin/comp.dc
/trunk/syn/bin/design_spec.dc
/trunk/syn/bin/lib_spec.dc
/trunk/syn/bin/read.dc