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[/] [can/] [tags/] [rel_10/] [sim/] - Rev 8

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Last modification

Rev 8, 2002-12-26 16:00:37 GMT
Author: mohor
Log message:
Testbench define file added. Clock divider register added.

Path
/trunk/bench/verilog/can_testbench.v
/trunk/bench/verilog/can_testbench_defines.v
/trunk/rtl/verilog/can_registers.v
/trunk/rtl/verilog/can_top.v
/trunk/sim/rtl_sim/run/wave.do

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