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[/] [common/] [tags/] [initial/] [generic_memories/] [rtl/] [verilog/] - Rev 12
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Last modification
- Rev 12, 2001-09-14 09:57:10 GMT
- Author: rherveille
- Log message:
- Major cleanup.
Files are now compliant to Altera & Xilinx memories.
Memories are now compatible, i.e. drop-in replacements.
Added synthesizeable generic FPGA description.
Created "generic_memories" cvs entry.
