URL
https://opencores.org/ocsvn/cpu65c02_true_cycle/cpu65c02_true_cycle/trunk
Subversion Repositories cpu65c02_true_cycle
[/] [cpu65c02_true_cycle/] [trunk/] [beta/] [rtl/] [verilog/] - Rev 24
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Last modification
- Rev 23, 2018-10-14 14:31:34 GMT
- Author: fpga_is_funny
- Log message:
- Added "beta" section to separate upcoming beta versions or release candidates from released versions.
The currently released version moved to "released".
The upcoming v2.00rc loaded into "beta" is a major release candidate containing performance improvements.
fmax is now typical from 110 MHz to 180 MHz even for low/middle cost FPGA devices. High end FPGA devices allow clock rates over 250 MHz now.
After many cycle count issues caused by description errors in original vendor documents, the v2.00rc testing processes (in progress) rely on the WDC 65C02 documentation and physical chips for reference now.
