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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 161
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Last modification
- Rev 161, 2002-09-09 13:03:13 GMT
- Author: mohor
- Log message:
- Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
