URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 40

Rev 40, 2002-02-05 16:44:39 GMT
Author: mohor
Log message:
Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.

Path
/trunk/rtl/verilog/eth_defines.v
/trunk/rtl/verilog/eth_fifo.v
/trunk/rtl/verilog/eth_wishbone.v