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[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] - Rev 63

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Last modification

  • Rev 63, 2006-06-12 18:53:02 GMT
  • Author: fisher5090
  • Log message:
    remove pad function added, using xilinx vp20 -6 as target FPGA, passes post place and route simulation

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