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URL https://opencores.org/ocsvn/genesys_ddr2/genesys_ddr2/trunk

Subversion Repositories genesys_ddr2

[/] [genesys_ddr2/] [trunk/] [bench/] - Rev 2

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Last modification

  • Rev 2, 2013-05-06 14:26:49 GMT
  • Author: oana.boncalo
  • Log message:
    Oana Boncalo - First upload of DDR2 mem controller
Path
/genesys_ddr2/trunk/bench
/genesys_ddr2/trunk/bench/test_DDR2_wb.v
/genesys_ddr2/trunk/bench/wishbone_mock.v
/genesys_ddr2/trunk/bench/Xilinx_MIG_bench
/genesys_ddr2/trunk/bench/Xilinx_MIG_bench/sim
/genesys_ddr2/trunk/bench/Xilinx_MIG_bench/sim/ddr2_adr_data_gen.v
/genesys_ddr2/trunk/bench/Xilinx_MIG_bench/sim/ddr2_tb_test_addr_gen.v
/genesys_ddr2/trunk/bench/Xilinx_MIG_bench/sim/ddr2_tb_test_cmp.v
/genesys_ddr2/trunk/bench/Xilinx_MIG_bench/sim/ddr2_tb_test_data_gen.v
/genesys_ddr2/trunk/bench/Xilinx_MIG_bench/sim/ddr2_tb_test_gen.v
/genesys_ddr2/trunk/bench/Xilinx_MIG_bench/sim/ddr2_tb_top.v
/genesys_ddr2/trunk/bench/Xilinx_MIG_bench/sim/ddr2_user_if_top.v
/genesys_ddr2/trunk/par
/genesys_ddr2/trunk/par/test_DDR2_wb.ucf
/genesys_ddr2/trunk/README.txt
/genesys_ddr2/trunk/rtl
/genesys_ddr2/trunk/rtl/clkGenPLL.v
/genesys_ddr2/trunk/rtl/DDR2_Mem.v
/genesys_ddr2/trunk/rtl/DDR2_mem_wb_if.v
/genesys_ddr2/trunk/rtl/debounceRst.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_chipscope.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_ctrl.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_idelay_ctrl.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_infrastructure.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_mem_if_top.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_phy_calib.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_phy_ctl_io.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_phy_dm_iob.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_phy_dqs_iob.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_phy_dq_iob.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_phy_init.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_phy_io.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_phy_top.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_phy_write.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_top.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_usr_addr_fifo.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_usr_rd.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_usr_top.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/ddr2_usr_wr.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/rtl/MEMCtrl.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/sim
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/sim/ddr2_adr_data_gen.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/sim/ddr2_tb_test_addr_gen.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/sim/ddr2_tb_test_cmp.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/sim/ddr2_tb_test_data_gen.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/sim/ddr2_tb_test_gen.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/sim/ddr2_tb_top.v
/genesys_ddr2/trunk/rtl/XilinxMIG_MemCtrl/user_design/sim/ddr2_user_if_top.v

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