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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] - Rev 62

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Last modification

Rev 62, 2011-04-29 10:32:37 GMT
Author: rfajardo
Log message:
Wrapping different family modules of same manufacturer in a single module.

minsoc_clock_manager.v: uses fpga manufacturer wrappers

xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

altera_pll.v: selects between different Altera FPGA families and implements the module

Path
/minsoc/trunk/rtl/verilog/altera_pll.v
/minsoc/trunk/rtl/verilog/minsoc_clock_manager.v
/minsoc/trunk/rtl/verilog/minsoc_pll.v
/minsoc/trunk/rtl/verilog/xilinx_dcm.v

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