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[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [altera_3c25_board/] - Rev 124
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Last modification
- Rev 124, 2011-11-02 15:27:24 GMT
- Author: rfajardo
- Log message:
- Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.
