URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] - Rev 27
Directory listing | View Log | Compare with Previous | RSS feed
Last modification
- Rev 27, 2010-04-20 14:14:15 GMT
- Author: rfajardo
- Log message:
- Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, which did not output its data.
The data was being output to doq instead of q, the declared output. doq was also not defined anywhere else.
Icarus Verilog did not detect this, because Verilog-2001 allows internal wires to be used without being defined. To detect this errors, one can define "`default_nettype none". After doing this, Icarus Verilog detected that error and nothing else.
doq changed to q, error corrected.
