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[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] - Rev 7

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Last modification

Rev 7, 2009-10-02 15:56:44 GMT
Author: rfajardo
Log message:
Some changes:
-wb_cabs removed from minsoc_top.v and minsoc_tc_top.v
-added reset polarity control to minsoc_defines.v through:
-POSITIVE_RESET
-NEGATIVE_RESET
-minsoc_onchip_ram_top.v does not use
minsoc_onchip_ram.v oe signals (output enable) anymore,
which are implemented as tristate buffers. Now
minsoc_onchip_ram_top.v has a generated MUX, which
has an arbitrary number of inputs and 1 output.
Input are the internal output of the onchip_rams,
output the wb_dat_o.

Path
/minsoc/trunk/bench/verilog/minsoc_bench_defines.v
/minsoc/trunk/rtl/verilog/minsoc_defines.v
/minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v
/minsoc/trunk/rtl/verilog/minsoc_onchip_ram_top.v
/minsoc/trunk/rtl/verilog/minsoc_tc_top.v
/minsoc/trunk/rtl/verilog/minsoc_top.v

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