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[/] [minsoc/] [branches/] [verilator/] - Rev 108
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Last modification
- Rev 108, 2011-10-26 16:48:51 GMT
- Author: rfajardo
- Log message:
- Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.
Icarus Verilog and Altera synthesis are working as well. Job done!
