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[/] [minsoc/] [branches/] [verilator/] - Rev 56

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Last modification

Rev 56, 2011-04-21 22:40:38 GMT
Author: javieralso
Log message:
Macros for all Altera family devices and pll instantiation

Path
/minsoc/trunk/rtl/verilog/minsoc_clock_manager.v
/minsoc/trunk/rtl/verilog/minsoc_defines.v
/minsoc/trunk/rtl/verilog/minsoc_pll.v
/minsoc/trunk/rtl/verilog/minsoc_top.v

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