Subversion Repositories minsoc

Last modification

• Rev 57, 2011-04-28 21:27:09 GMT
• Author: rfajardo

• Log message:

  If a FPGA manufacturer is selected, the FPGA families of other manufacturers are automatically ignored.
  
  Some updated to comments.
  
  CLOCK_DIVISOR back to 5. The number does not matter much, but 1 is a bad standard number, since it should never be selected. Comment says, use NO_CLOCK_DIVISION instead.
  
  Changing standard FPGA back to Xilinx and Spartan3A. I'm only doing this because the synthesis examples page of wiki still assume this FPGA to be standardly selected.