URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [backend/] - Rev 124

Rev 124, 2011-11-02 15:27:24 GMT
Author: rfajardo
Log message:
Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.

Path
/minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v
/minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v
/minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v
/minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v
/minsoc/branches/rc-1.0/backend/std/minsoc_bench_defines.v
/minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v