URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [bench/] - Rev 60

Rev 60, 2011-04-28 22:44:09 GMT
Author: rfajardo
Log message:
Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation.

minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition.

Path
/minsoc/trunk/bench/verilog/minsoc_bench.v
/minsoc/trunk/bench/verilog/minsoc_bench_defines.v
/minsoc/trunk/bench/verilog/minsoc_memory_model.v
/minsoc/trunk/rtl/verilog/minsoc_top.v
/minsoc/trunk/sim/bin/minsoc_memory.txt
/minsoc/trunk/sim/bin/minsoc_model.txt
/minsoc/trunk/sim/bin/minsoc_verilog_files.txt
/minsoc/trunk/sim/run/generate_bench