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[/] [minsoc/] [branches/] [verilator/] [sim/] [modelsim/] - Rev 132
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Last modification
- Rev 132, 2011-11-03 14:10:18 GMT
- Author: rfajardo
- Log message:
- ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench.
