URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [sim/] [modelsim/] - Rev 133

Rev 133, 2011-11-07 09:48:11 GMT
Author: rfajardo
Log message:
Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.

Applying Rubén Diez patch to avoid warnings on firmware load for simulation.

Path
/minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v
/minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_core.v
/minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj
/minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat
/minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh
/minsoc/branches/rc-1.0/sim/run/run_bench
/minsoc/branches/rc-1.0/sw/utils/bin2hex.c