URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 89

Rev 89, 2013-04-24 20:19:10 GMT
Author: JonasDC
Log message:
updated vhdl files so now different clock frequencies are posible for the core and bus interface.

Path
/mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd
/mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
/mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd
/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd
/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd
/mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd
/mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd