URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 39

Rev 39, 2012-11-12 21:18:13 GMT
Author: JonasDC
Log message:
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic

Path
/mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/sys_last_cell_logic.vhd