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[/] [neorv32/] [trunk/] [sw/] [lib/] - Rev 52

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Last modification

  • Rev 52, 2021-03-08 12:28:15 GMT
  • Author: zero_gravity
  • Log message:
    bump to version 1.5.2.4
    see CHANGELOG.md for more information
Path
/neorv32/trunk/.ci/install.sh
/neorv32/trunk/CHANGELOG.md
/neorv32/trunk/docs/figures/neorv32_processor.png
/neorv32/trunk/docs/NEORV32.pdf
/neorv32/trunk/README.md
/neorv32/trunk/riscv-arch-test
/neorv32/trunk/riscv-arch-test/port-neorv32
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/compliance_io.h
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/compliance_test.h
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/device
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/device/.ld_script
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/device/.ld_script/link.ld
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32i
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32i/Makefile.include
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32im
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32im/Makefile.include
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32imc
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32imc/Makefile.include
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32Zicsr
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32Zicsr/Makefile.include
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32Zifencei
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32Zifencei/Makefile.include
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v1.0/riscv-target/neorv32/README.md
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/device
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/C
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/C/Makefile.include
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/I
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/I/Makefile.include
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/M
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/M/Makefile.include
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/privilege
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/privilege/Makefile.include
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/Zifencei
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/Zifencei/Makefile.include
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/link.imem_ram.ld
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/link.imem_rom.ld
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/model_test.h
/neorv32/trunk/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/README.md
/neorv32/trunk/riscv-arch-test/README.md
/neorv32/trunk/riscv-arch-test/run_riscv_arch_test.sh
/neorv32/trunk/riscv-arch-test/work
/neorv32/trunk/riscv-arch-test/work/.gitignore
/neorv32/trunk/riscv-compliance
/neorv32/trunk/rtl/core/neorv32_cfs.vhd
/neorv32/trunk/rtl/core/neorv32_cpu.vhd
/neorv32/trunk/rtl/core/neorv32_cpu_control.vhd
/neorv32/trunk/rtl/core/neorv32_cpu_cp_fpu.vhd
/neorv32/trunk/rtl/core/neorv32_cpu_decompressor.vhd
/neorv32/trunk/rtl/core/neorv32_neoled.vhd
/neorv32/trunk/rtl/core/neorv32_package.vhd
/neorv32/trunk/rtl/core/neorv32_sysinfo.vhd
/neorv32/trunk/rtl/core/neorv32_top.vhd
/neorv32/trunk/rtl/top_templates/neorv32_test_setup.vhd
/neorv32/trunk/rtl/top_templates/neorv32_top_axi4lite.vhd
/neorv32/trunk/rtl/top_templates/neorv32_top_stdlogic.vhd
/neorv32/trunk/sim/ghdl/ghdl_sim.sh
/neorv32/trunk/sim/neorv32_tb.vhd
/neorv32/trunk/sw/common/crt0.S
/neorv32/trunk/sw/example/bit_manipulation/README.md
/neorv32/trunk/sw/example/demo_gpio_irq/main.c
/neorv32/trunk/sw/example/demo_neopixel
/neorv32/trunk/sw/example/demo_neopixel/main.c
/neorv32/trunk/sw/example/demo_neopixel/makefile
/neorv32/trunk/sw/lib/include/neorv32.h
/neorv32/trunk/sw/lib/include/neorv32_neoled.h
/neorv32/trunk/sw/lib/source/neorv32_neoled.c
/neorv32/trunk/sw/lib/source/neorv32_rte.c
/neorv32/trunk/sw/lib/source/neorv32_spi.c

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