URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] - Rev 223

Rev 223, 2020-04-15 22:12:24 GMT
Author: jshamlet
Log message:
Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up.

Path
/open8_urisc/trunk/VHDL/o8_alu16.vhd
/open8_urisc/trunk/VHDL/o8_async_serial.vhd
/open8_urisc/trunk/VHDL/o8_btn_int.vhd
/open8_urisc/trunk/VHDL/o8_clk_detect.vhd
/open8_urisc/trunk/VHDL/o8_cpu.vhd
/open8_urisc/trunk/VHDL/o8_crc16_ccitt.vhd
/open8_urisc/trunk/VHDL/o8_datalatch.vhd
/open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
/open8_urisc/trunk/VHDL/o8_epoch_timer_ii.vhd
/open8_urisc/trunk/VHDL/o8_gpin.vhd
/open8_urisc/trunk/VHDL/o8_gpio.vhd
/open8_urisc/trunk/VHDL/o8_gpout.vhd
/open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd
/open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd
/open8_urisc/trunk/VHDL/o8_lfsr32.vhd
/open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd
/open8_urisc/trunk/VHDL/o8_max7221.vhd
/open8_urisc/trunk/VHDL/o8_pwm16.vhd
/open8_urisc/trunk/VHDL/o8_ram_1k.vhd
/open8_urisc/trunk/VHDL/o8_ram_4k.vhd
/open8_urisc/trunk/VHDL/o8_register.vhd
/open8_urisc/trunk/VHDL/o8_rom_32k.vhd
/open8_urisc/trunk/VHDL/o8_rtc.vhd
/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
/open8_urisc/trunk/VHDL/o8_status_led.vhd
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd
/open8_urisc/trunk/VHDL/o8_vdsm8.vhd
/open8_urisc/trunk/VHDL/o8_vdsm12.vhd
/open8_urisc/trunk/VHDL/Open8_pkg.vhd