URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 246

Rev 246, 2020-05-23 17:36:40 GMT
Author: jshamlet
Log message:
The system timer module now allows for an optional millisecond resolution (settable through a generic). This prescalar enable permits the timer to operate from 1 to 256 mS, which is useful for a variety of tasks, such as serial timeouts and watchdog timers. The enable is not software settable, as this would complicate the register interface and isn't generally useful in an HDL based SOC design.

The vector interface now has a parallel interface that runs beside the serial interface, and is useful for connecting to DIO cards or other parallel interfaces.

Path
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd
/open8_urisc/trunk/VHDL/o8_vector_rx.vhd