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[/] [openmsp430/] - Rev 145

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Last modification

  • Rev 145, 2012-05-30 21:03:05 GMT
  • Author: olivier.girard
  • Log message:
    Add Dhrystone and CoreMark benchmarks to the simulation environment.
Path
/openmsp430/trunk/core/bench/verilog/registers.v
/openmsp430/trunk/core/sim/rtl_sim/run/run_c
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark.md5
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark_v1.0.v
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_list_join.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_main.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_matrix.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_state.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_util.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/docs
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/docs/Coremark-requirements.doc
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/docs/LICENSE.DOC
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/docs/r01an0757eu_rx.pdf
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/LICENSE.txt
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/Makefile
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/core_portme.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/core_portme.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/core_portme.mak
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/omsp_func.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/omsp_func.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/readme.txt
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/release_notes.txt
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhry.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhry21a.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhry21b.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhrystone_4mcu.v
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/makefile
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/omsp_func.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/omsp_func.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/dhry.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/dhry21a.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/dhry21b.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/Dhrystone.pnproj
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/dhyrstone.pro
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/estubs.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/Makefile
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/ReadMe.txt
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/timers_b.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/z8obj
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhrystone_v2.1.v
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry_1.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry_2.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/doc
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/doc/reu05b0134_rxap.pdf
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/makefile
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/omsp_func.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/omsp_func.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/bymanuf
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/byperf
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/cc_dry2
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/cc_dry2reg
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/clarify.doc
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry-2.1.p
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry.p
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry_1.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry_2.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry_c.dif
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/doit
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/Makefile
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/pure2_1.dif
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/RATIONALE
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/README
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/README.RER
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/results
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/submit.frm
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/sandbox.v
/openmsp430/trunk/core/sim/rtl_sim/src/ldscript_example.x

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