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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] - Rev 180
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Last modification
- Rev 180, 2013-02-25 21:23:18 GMT
- Author: olivier.girard
- Log message:
- Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)