URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] - Rev 84

Rev 84, 2011-01-23 20:00:36 GMT
Author: olivier.girard
Log message:
Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.

Path
/openmsp430/trunk/core/bench/verilog/ram.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
/openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/hardware.c
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/main.c