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[/] [openmsp430/] [trunk/] [core/] [sim/] - Rev 154

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Last modification

  • Rev 154, 2012-10-15 20:44:20 GMT
  • Author: olivier.girard
  • Log message:
    The serial debug interface now supports the I2C protocol (in addition to the UART)
Path
/openmsp430/trunk/core/bench/verilog/dbg_i2c_tasks.v
/openmsp430/trunk/core/bench/verilog/dbg_uart_tasks.v
/openmsp430/trunk/core/bench/verilog/io_cell.v
/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg_i2c.v
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v
/openmsp430/trunk/core/rtl/verilog/openMSP430.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
/openmsp430/trunk/core/sim/rtl_sim/bin/template_defs.asm
/openmsp430/trunk/core/sim/rtl_sim/run
/openmsp430/trunk/core/sim/rtl_sim/run/run_all
/openmsp430/trunk/core/sim/rtl_sim/src/core.f
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_cpu.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_cpu.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_halt_irq.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_halt_irq.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk0.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk0.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk1.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk1.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk2.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk2.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk3.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk3.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_rdwr.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_rdwr.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_sync.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_sync.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_cpu.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_cpu.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_halt_irq.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_halt_irq.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk0.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk0.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk1.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk1.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk2.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk2.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk3.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk3.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_rdwr.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_rdwr.v
/openmsp430/trunk/core/sim/rtl_sim/src/sfr.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sfr.v
/openmsp430/trunk/core/sim/rtl_sim/src/submit.f
/openmsp430/trunk/core/sim/rtl_sim/src/submit.prj

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