URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] - Rev 175

Rev 175, 2013-01-30 21:21:42 GMT
Author: olivier.girard
Log message:
Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports.

Path
/openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v
/openmsp430/trunk/core/rtl/verilog/openMSP430.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk0.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk1.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk2.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk3.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_rdwr.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk0.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk1.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk2.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk3.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_rdwr.v
/openmsp430/trunk/core/synthesis/synopsys/read.tcl