URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] - Rev 103

Rev 103, 2011-03-05 14:44:48 GMT
Author: olivier.girard
Log message:
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.

Path
/openmsp430/trunk/core/bench/verilog/msp_debug.v
/openmsp430/trunk/core/bench/verilog/ram.v
/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
/openmsp430/trunk/core/bench/verilog/timescale.v
/openmsp430/trunk/core/rtl/verilog/omsp_alu.v
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v
/openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v
/openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v
/openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v
/openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v
/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v
/openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
/openmsp430/trunk/core/rtl/verilog/openMSP430.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v
/openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v
/openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v
/openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
/openmsp430/trunk/core/rtl/verilog/timescale.v
/openmsp430/trunk/core/sim/rtl_sim/src/submit.f