URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] - Rev 86

Rev 86, 2011-01-28 22:53:28 GMT
Author: olivier.girard
Log message:
Update serial debug interface test patterns to make them work with all program memory configurations.

Path
/openmsp430/trunk/core/rtl/verilog/openMSP430.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v