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[/] [openmsp430/] [trunk/] [fpga/] - Rev 200

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Last modification

  • Rev 200, 2015-01-21 22:01:31 GMT
  • Author: olivier.girard
  • Log message:
    Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains.
Path
/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
/openmsp430/trunk/core/rtl/verilog/openMSP430.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
/openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
/openmsp430/trunk/core/sim/rtl_sim/bin/template_defs.asm
/openmsp430/trunk/core/sim/rtl_sim/run/run
/openmsp430/trunk/core/sim/rtl_sim/run/run_all
/openmsp430/trunk/core/sim/rtl_sim/run/run_all_mpy
/openmsp430/trunk/core/sim/rtl_sim/run/run_c
/openmsp430/trunk/core/sim/rtl_sim/run/run_disassemble
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark_v1.0.v
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/copydata.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/core_portme.mak
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.msp430-elf.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.msp430.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/omsp_func.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/copydata.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhry.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhrystone_4mcu.v
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.msp430-elf.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.msp430.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/makefile
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/omsp_func.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/z8obj
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/copydata.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhrystone_v2.1.v
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry_1.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.msp430-elf.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.msp430.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/makefile
/openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/omsp_func.h
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/copydata.c
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.msp430-elf.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.msp430.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile
/openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/omsp_system.h
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_sync.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.s43
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.v
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/nmi.v
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.s43
/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.s43
/openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_add_rom-rd.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr-b.v
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr.v
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43
/openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43
/openmsp430/trunk/core/synthesis/synopsys/results
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/tmp
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem_xdb
/openmsp430/trunk/core/synthesis/xilinx/src/coregen/_xmsgs
/openmsp430/trunk/doc/toolchain_benchmark.txt
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/xlnx_auto_0_xdb
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/coregen/tmp
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v

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