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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x1k_dp/] [simulation/] - Rev 167

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Last modification

  • Rev 167, 2012-12-06 21:04:46 GMT
  • Author: olivier.girard
  • Log message:
    Update LX9 Microboard FPGA example.
    It now includes a dual-core oMSP system with a shared 16kB program memory.
    Each core has its own 2kB data memory and an additional 2kB shared data memory.
Path
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/msp_debug.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/ram.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/ram_16x1k_dp.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/ram_16x1k_sp.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/ram_16x2k.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/ram_16x8k_dp.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/ram_16x512.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/ram_dp.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/ram_sp.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/registers.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/registers_omsp0.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/registers_omsp1.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/tb_openMSP430_fpga.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/coregen.cgc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/coregen.log
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp.asy
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp.gise
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp.ngc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp.veo
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp.xco
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp.xise
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/blk_mem_gen_v7_2_readme.txt
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/doc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/doc/blk_mem_gen_v7_2_vinfo.html
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/doc/pg058-blk-mem-gen.pdf
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/example_design
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/example_design/ram_16x1k_dp_exdes.ucf
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/example_design/ram_16x1k_dp_exdes.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/example_design/ram_16x1k_dp_exdes.xdc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/example_design/ram_16x1k_dp_prod.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/implement
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/implement/implement.bat
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/implement/implement.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/implement/planAhead_ise.bat
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/implement/planAhead_ise.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/implement/planAhead_ise.tcl
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/implement/xst.prj
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/implement/xst.scr
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/addr_gen.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/bmg_stim_gen.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/bmg_tb_pkg.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/checker.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/data_gen.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/functional
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/functional/simcmds.tcl
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/functional/simulate_isim.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/functional/simulate_mti.bat
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/functional/simulate_mti.do
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/functional/simulate_mti.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/functional/simulate_ncsim.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/functional/simulate_vcs.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/functional/ucli_commands.key
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/functional/vcs_session.tcl
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/functional/wave_mti.do
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/functional/wave_ncsim.sv
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/ram_16x1k_dp_synth.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/ram_16x1k_dp_tb.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/random.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/timing
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/timing/simcmds.tcl
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/timing/simulate_isim.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/timing/simulate_mti.bat
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/timing/simulate_mti.do
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/timing/simulate_mti.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/timing/simulate_ncsim.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/timing/simulate_vcs.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/timing/ucli_commands.key
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/timing/vcs_session.tcl
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/timing/wave_mti.do
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/timing/wave_ncsim.sv
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp_flist.txt
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp_synth.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp_xmdf.tcl
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp.asy
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp.gise
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp.ngc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp.veo
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp.xco
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp.xise
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/blk_mem_gen_v7_2_readme.txt
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/doc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/doc/blk_mem_gen_v7_2_vinfo.html
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/doc/pg058-blk-mem-gen.pdf
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/example_design
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/example_design/ram_16x1k_sp_exdes.ucf
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/example_design/ram_16x1k_sp_exdes.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/example_design/ram_16x1k_sp_exdes.xdc
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/example_design/ram_16x1k_sp_prod.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/implement
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/implement/implement.bat
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/implement/implement.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/implement/planAhead_ise.bat
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/implement/planAhead_ise.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/implement/planAhead_ise.tcl
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/implement/xst.prj
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/implement/xst.scr
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/addr_gen.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/bmg_stim_gen.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/bmg_tb_pkg.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/checker.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/data_gen.vhd
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/functional
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/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/functional/simulate_isim.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/functional/simulate_mti.bat
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/functional/simulate_mti.do
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/functional/simulate_mti.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/functional/simulate_ncsim.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/functional/simulate_vcs.sh
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/functional/ucli_commands.key
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/functional/vcs_session.tcl
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/functional/wave_mti.do
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/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/random.vhd
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/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/timing/simulate_ncsim.sh
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