URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [bin/] - Rev 151

Rev 151, 2012-07-22 22:24:11 GMT
Author: olivier.girard
Log message:
Add possibility to configure custom Program, Data and Peripheral memory sizes.

Path
/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
/openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
/openmsp430/trunk/core/sim/rtl_sim/bin/omsp_config.sh
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v
/openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43
/openmsp430/trunk/doc/openMSP430.odt
/openmsp430/trunk/doc/openMSP430.pdf
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/omsp_config.sh
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/omsp_config.sh
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/omsp_config.sh