URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [bin/] - Rev 98

Rev 98, 2011-02-28 20:20:51 GMT
Author: olivier.girard
Log message:
Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.

Path
/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
/openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/rtlsim.sh
/openmsp430/trunk/fpga/altera_de1_board/bench/verilog/tb_openMSP430_fpga.v
/openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/rtlsim.sh
/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/tb_openMSP430_fpga.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/rtlsim.sh