URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [src/] - Rev 26

Rev 26, 2009-12-19 12:25:10 GMT
Author: olivier.girard
Log message:
Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.

Path
/openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/openmsp430
/openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/timescale.v
/openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/bin/msp430sim
/openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/src/submit.f
/openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.bat
/openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream.sh
/openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga.prj
/openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga.ucf
/openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga_top.ucf
/openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga_top.v
/openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/xst_verilog.opt