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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [software/] [ta_uart/] - Rev 153

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Last modification

  • Rev 153, 2012-08-21 22:27:18 GMT
  • Author: olivier.girard
  • Log message:
    Update XFLOW scripts to bring more automation.
    Several bitstreams are now checked in for direct use.
Path
/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/tb_openMSP430_fpga.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/run
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/hw_uart.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/ta_uart.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/software/ta_uart/main.c
/openmsp430/trunk/fpga/xilinx_diligent_s3board/software/ta_uart/swuart.h
/openmsp430/trunk/fpga/xilinx_diligent_s3board/software/ta_uart/swuart.s
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/0_create_bitstream.sh
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/1_initialize_pmem.sh
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/2_generate_prom_file.sh
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/3_program_fpga.sh
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/hw_uart.bit
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/hw_uart.mcs
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/leds.bit
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/leds.mcs
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/openMSP430_fpga.bit
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/openMSP430_fpga.mcs
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/README.jpg
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/ta_uart.bit
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/bitstreams/ta_uart.mcs
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/create_bitstream.bat
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/create_bitstream.sh
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/load_pmem.bat
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/load_pmem.sh
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/memory.bmm
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/openMSP430_fpga.prj
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/openMSP430_fpga.ucf
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/ihex2mem.tcl
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/impact_generate_prom_file.batch
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/impact_program_fpga.batch
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/memory.bmm
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/openMSP430_fpga.prj
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/openMSP430_fpga.ucf
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/xst_verilog.opt
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/win_0_create_bitstream.bat
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/win_1_initialize_pmem.bat
/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/xst_verilog.opt

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