URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [branches/] [or1200_rel3/] [rtl/] [verilog/] - Rev 185

Rev 185, 2010-07-11 15:28:17 GMT
Author: julius
Log message:
Adding single precision FPU to or1200, initial checkin, not fully tested yet

Path
/openrisc/trunk/bootloaders/orpmon/include/board.h
/openrisc/trunk/bootloaders/orpmon/include/build.h
/openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_amultp2_32x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_cfgr.v
/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
/openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
/openrisc/trunk/or1200/rtl/verilog/or1200_du.v
/openrisc/trunk/or1200/rtl/verilog/or1200_except.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v
/openrisc/trunk/or1200/rtl/verilog/or1200_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_wbmux.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/Makefile