OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [branches/] [or1200_rel3/] [rtl/] [verilog/] - Rev 258

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 258, 2010-08-30 23:32:25 GMT
  • Author: julius
  • Log message:
    Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off
Path
/openrisc/trunk/or1200/doc/openrisc1200_spec.doc
/openrisc/trunk/or1200/doc/openrisc1200_spec.odt
/openrisc/trunk/or1200/doc/openrisc1200_spec.pdf
/openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_amultp2_32x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_cfgr.v
/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dc_ram.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dc_tag.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dc_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dmmu_tlb.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dmmu_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dpram.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dpram_256x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_du.v
/openrisc/trunk/or1200/rtl/verilog/or1200_except.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_addsub.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_arith.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_div.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_fcmp.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_intfloat_conv.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_mul.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_addsub.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_div.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_mul.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_pre_norm_addsub.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_pre_norm_div.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu_pre_norm_mul.v
/openrisc/trunk/or1200/rtl/verilog/or1200_freeze.v
/openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
/openrisc/trunk/or1200/rtl/verilog/or1200_gmultp2_32x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_ic_fsm.v
/openrisc/trunk/or1200/rtl/verilog/or1200_ic_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_if.v
/openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_iwb_biu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_lsu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
/openrisc/trunk/or1200/rtl/verilog/or1200_operandmuxes.v
/openrisc/trunk/or1200/rtl/verilog/or1200_pic.v
/openrisc/trunk/or1200/rtl/verilog/or1200_pm.v
/openrisc/trunk/or1200/rtl/verilog/or1200_qmem_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_rf.v
/openrisc/trunk/or1200/rtl/verilog/or1200_rfram_generic.v
/openrisc/trunk/or1200/rtl/verilog/or1200_sb.v
/openrisc/trunk/or1200/rtl/verilog/or1200_sb_fifo.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_32x24.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_32_bw.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x14.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x22.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_128x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_256x21.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x8.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x8.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
/openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v
/openrisc/trunk/or1200/rtl/verilog/or1200_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_tt.v
/openrisc/trunk/or1200/rtl/verilog/or1200_wbmux.v
/openrisc/trunk/or1200/rtl/verilog/or1200_wb_biu.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.