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[/] [openrisc/] [trunk/] - Rev 69

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Last modification

  • Rev 69, 2010-02-19 03:25:04 GMT
  • Author: julius
  • Log message:
    ORPSoC xilinx ml501 board update - added ethernet eupport and software test
Path
/openrisc/trunk/orpsocv2/bench/verilog/eth_phy_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/par/ml501_xst.ucf
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/eth_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_mc.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_startup.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board.h
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/eth.c
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/eth.ld
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/eth_reset.S
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/except.S
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/mii.h
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/open_eth.h
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/memtest.c
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/Makefile
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/BUGS
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_cop.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_wishbone.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/filer
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/Makefile
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/TODO
/openrisc/trunk/orpsocv2/sim/bin/Makefile

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