OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] - Rev 358

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 358, 2010-09-10 09:00:43 GMT
  • Author: julius
  • Log message:
    OR1200's reset now configurable as active high or active low. Thanks to patch
    from OpenCores contributor Kuoping.

    Updated OR1200 in ORPSoCv2 and OR1200 project.
Path
/openrisc/trunk/or1200/rtl/verilog/or1200_amultp2_32x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v
/openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dmmu_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dpram_256x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_du.v
/openrisc/trunk/or1200/rtl/verilog/or1200_except.v
/openrisc/trunk/or1200/rtl/verilog/or1200_fpu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_freeze.v
/openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
/openrisc/trunk/or1200/rtl/verilog/or1200_gmultp2_32x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_ic_fsm.v
/openrisc/trunk/or1200/rtl/verilog/or1200_if.v
/openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_lsu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
/openrisc/trunk/or1200/rtl/verilog/or1200_operandmuxes.v
/openrisc/trunk/or1200/rtl/verilog/or1200_pic.v
/openrisc/trunk/or1200/rtl/verilog/or1200_pm.v
/openrisc/trunk/or1200/rtl/verilog/or1200_qmem_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_rf.v
/openrisc/trunk/or1200/rtl/verilog/or1200_rfram_generic.v
/openrisc/trunk/or1200/rtl/verilog/or1200_sb.v
/openrisc/trunk/or1200/rtl/verilog/or1200_sb_fifo.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_32x24.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x14.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x22.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_128x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_256x21.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x8.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x8.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
/openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v
/openrisc/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_tt.v
/openrisc/trunk/or1200/rtl/verilog/or1200_wbmux.v
/openrisc/trunk/or1200/rtl/verilog/or1200_wb_biu.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_amultp2_32x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dc_fsm.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dmmu_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dpram_32x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dpram_256x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_du.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_except.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_fpu.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_freeze.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_genpc.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_gmultp2_32x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_ic_fsm.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_if.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_immu_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_lsu.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_operandmuxes.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_pic.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_pm.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_qmem_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_rf.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_rfram_generic.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_sb.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_sb_fifo.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_spram_32x24.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_spram_64x14.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_spram_64x22.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_spram_64x24.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_spram_128x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_spram_256x21.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_spram_512x20.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_spram_1024x8.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_spram_1024x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_spram_1024x32_bw.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_spram_2048x8.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_spram_2048x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_spram_2048x32_bw.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_tpram_32x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_tt.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_wbmux.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_wb_biu.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v
/openrisc/trunk/orpsocv2/sw/include/or1200-defines.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.