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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [lib/] - Rev 10

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Last modification

  • Rev 10, 2009-05-25 08:01:12 GMT
  • Author: unneback
  • Log message:
    or1200 added from or1k subversion repository
Path
/openrisc/trunk/or1200
/openrisc/trunk/or1200/bench
/openrisc/trunk/or1200/bench/README
/openrisc/trunk/or1200/doc
/openrisc/trunk/or1200/doc/openrisc1200_spec.doc
/openrisc/trunk/or1200/doc/openrisc1200_spec.pdf
/openrisc/trunk/or1200/lib
/openrisc/trunk/or1200/lib/README
/openrisc/trunk/or1200/lint
/openrisc/trunk/or1200/lint/bin
/openrisc/trunk/or1200/lint/bin/README
/openrisc/trunk/or1200/lint/bin/run_lint
/openrisc/trunk/or1200/lint/log
/openrisc/trunk/or1200/lint/log/README
/openrisc/trunk/or1200/lint/run
/openrisc/trunk/or1200/lint/run/README
/openrisc/trunk/or1200/rtl
/openrisc/trunk/or1200/rtl/verilog
/openrisc/trunk/or1200/rtl/verilog/or1200_alu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_amultp2_32x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_cfgr.v
/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dc_ram.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dc_tag.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dc_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_defines.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dmmu_tlb.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dmmu_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_dpram_256x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_du.v
/openrisc/trunk/or1200/rtl/verilog/or1200_except.v
/openrisc/trunk/or1200/rtl/verilog/or1200_freeze.v
/openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
/openrisc/trunk/or1200/rtl/verilog/or1200_gmultp2_32x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_ic_fsm.v
/openrisc/trunk/or1200/rtl/verilog/or1200_ic_ram.v
/openrisc/trunk/or1200/rtl/verilog/or1200_ic_tag.v
/openrisc/trunk/or1200/rtl/verilog/or1200_ic_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_if.v
/openrisc/trunk/or1200/rtl/verilog/or1200_immu_tlb.v
/openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_iwb_biu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_lsu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_mem2reg.v
/openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
/openrisc/trunk/or1200/rtl/verilog/or1200_operandmuxes.v
/openrisc/trunk/or1200/rtl/verilog/or1200_pic.v
/openrisc/trunk/or1200/rtl/verilog/or1200_pm.v
/openrisc/trunk/or1200/rtl/verilog/or1200_qmem_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_reg2mem.v
/openrisc/trunk/or1200/rtl/verilog/or1200_rf.v
/openrisc/trunk/or1200/rtl/verilog/or1200_rfram_generic.v
/openrisc/trunk/or1200/rtl/verilog/or1200_sb.v
/openrisc/trunk/or1200/rtl/verilog/or1200_sb_fifo.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_32x24.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x14.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x22.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x24.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_128x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_256x21.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_512x20.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x8.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x8.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
/openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v
/openrisc/trunk/or1200/rtl/verilog/or1200_top.v
/openrisc/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v
/openrisc/trunk/or1200/rtl/verilog/or1200_tt.v
/openrisc/trunk/or1200/rtl/verilog/or1200_wbmux.v
/openrisc/trunk/or1200/rtl/verilog/or1200_wb_biu.v
/openrisc/trunk/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
/openrisc/trunk/or1200/rtl/verilog/timescale.v
/openrisc/trunk/or1200/sim
/openrisc/trunk/or1200/sim/README
/openrisc/trunk/or1200/syn
/openrisc/trunk/or1200/syn/synopsys
/openrisc/trunk/or1200/syn/synopsys/bin
/openrisc/trunk/or1200/syn/synopsys/bin/README
/openrisc/trunk/or1200/syn/synopsys/bin/read_design.inc
/openrisc/trunk/or1200/syn/synopsys/bin/run_syn
/openrisc/trunk/or1200/syn/synopsys/bin/top.scr
/openrisc/trunk/or1200/syn/synopsys/log
/openrisc/trunk/or1200/syn/synopsys/log/README
/openrisc/trunk/or1200/syn/synopsys/out
/openrisc/trunk/or1200/syn/synopsys/out/README
/openrisc/trunk/or1200/syn/synopsys/run
/openrisc/trunk/or1200/syn/synopsys/run/README

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