URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [common/] - Rev 220

Rev 220, 2010-07-23 19:15:28 GMT
Author: jeremybennett
Log message:
Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this.

Path
/openrisc/trunk/or1ksim/ChangeLog
/openrisc/trunk/or1ksim/config.h.in
/openrisc/trunk/or1ksim/configure
/openrisc/trunk/or1ksim/configure.ac
/openrisc/trunk/or1ksim/cpu/common/abstract.c
/openrisc/trunk/or1ksim/cpu/common/parse.c
/openrisc/trunk/or1ksim/cpu/or1k/opcode/or32.h
/openrisc/trunk/or1ksim/cpu/or32/generate.c
/openrisc/trunk/or1ksim/cpu/or32/insnset.c
/openrisc/trunk/or1ksim/cpu/or32/or32.c
/openrisc/trunk/or1ksim/doc/or1ksim.info
/openrisc/trunk/or1ksim/doc/version.texi
/openrisc/trunk/or1ksim/libtoplevel.c
/openrisc/trunk/or1ksim/or1ksim.h
/openrisc/trunk/or1ksim/pic/pic.c
/openrisc/trunk/or1ksim/sim-config.c
/openrisc/trunk/or1ksim/sim-config.h
/openrisc/trunk/or1ksim/testsuite/ChangeLog
/openrisc/trunk/or1ksim/testsuite/libsim.tests/jtag-write-control.exp
/openrisc/trunk/or1ksim/testsuite/libsim.tests/upcalls.exp
/openrisc/trunk/or1ksim/testsuite/or1ksim.tests/except-test.exp
/openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/lib-iftest.c
/openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/lib-inttest-edge.c
/openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/lib-inttest-level.c
/openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/lib-jtag-full.c
/openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/lib-jtag.c
/openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/lib-upcalls.c
/openrisc/trunk/or1ksim/toplevel-support.c