OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] - Rev 385

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 385, 2010-10-02 14:15:12 GMT
  • Author: jeremybennett
  • Log message:
    Updates for Or1ksim 0.5.0rc2.

    * configure: Regenerated.
    * configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
    * debug/rsp-server.c (rsp_query): Simplified handling of
    "qTStatus" to indicate we just do not support tracing.
    * doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
    specify the target.
    <Memory Configuration>: Warns about issues with memory controller.
    <Memory Controller Configuration>: Warns about issues with memory
    controller and advises not to use it.
    <Standalone Simulator>: Details for options with arguments updated.
    * NEWS: Updated for 0.5.0rc2.
    * peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
    (mc_index): Ensure value is valid.
    * peripheral/mc-defines.h <MC_CE_VALID>: Defined.

    * testsuite/test-code-or1k/configure: Regenerated.
    * testsuite/test-code-or1k/configure.ac: Handle the case where
    target_cpu is not set. Version changed to 0.5.0rc2.
    * testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
    Definition corrected.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.