OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] - Rev 230

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 230, 2010-08-01 18:29:47 GMT
  • Author: jeremybennett
  • Log message:
    Changed library interface. Fixed namespace problems with instruction lookup in library.

    * configure: Regenerated.
    * configure.ac: Version changed to current date.
    * cpu/or1k/opcode/or32.h <or1ksim_build_automata>: Renamed from
    build_automata.
    <l_none, num_opcodes, insn_index>: Deleted.
    <or1ksim_op_start>: Renamed from op_start.
    <or1ksim_automata>: Renamed from automata.
    <or1ksim_ti>: Renamed from ti.
    <or1ksim_or32_opcodes>: Renamed from or32_opcodes.
    <or1ksim_disassembled>: Renamed from disassembled.
    <or1ksim_insn_len>: Renamed from insn_len.
    <or1ksim_insn_name>: Renamed from insn_name.
    <or1ksim_destruct_automata>: Renamed from destruct_automata.
    <or1ksim_insn_decode>: Renamed from insn_decode.
    <or1ksim_disassemble_insn>: Renamed from disassemble_insn.
    <or1ksim_disassemble_index>: Renamed from disassemble_index.
    <or1ksim_extend_imm>: Renamed from extend_imm.
    <or1ksim_or32_extract>: Renamed from or32_extract
    * cpu/or32/or32.c, cpu/or32/execute.c, cpu/or32/generate.c,
    * cpu/common/stats.c, cpu/common/abstract.c, cpu/common/parse.c,
    * cpu/or1k/opcode/or32.h, cuc/load.c, cuc/cuc.c,
    * support/dumpverilog.c, toplevel-support.c: Renaming
    corresponding to changes in cpu/or1k/opcode/or32.h.
    * cpu/or32/execute-fp.h: Deleted
    * cpu/or32/generate.c <include_strings>: Remove reference to
    execute-fp.h
    * cpu/or32/execute.c <host_fp_rm>: Declared static.
    (fp_set_flags_restore_host_rm, fp_set_or1k_rm): Declared static,
    forward declaration removed.
    * or1ksim.h (or1ksim_read_mem, or1ksim_write_mem): addr arg
    changed to unsigned long int.
    (or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
    (or1ksim_write_spr): sprval arg changed to unsigned long int.
    (or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
    (or1ksim_write_reg): regval arg changed to unsigned long int.
    * libtoplevel.c (or1ksim_read_mem, or1ksim_write_mem): addr arg
    changed to unsigned long int.
    (or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
    (or1ksim_write_spr): sprval arg changed to unsigned long int.
    (or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
    (or1ksim_write_reg): regval arg changed to unsigned long int.
Path
/openrisc/trunk/or1ksim/aclocal.m4
/openrisc/trunk/or1ksim/argtable2/Makefile.in
/openrisc/trunk/or1ksim/bpb/Makefile.in
/openrisc/trunk/or1ksim/cache/Makefile.in
/openrisc/trunk/or1ksim/ChangeLog
/openrisc/trunk/or1ksim/config.h.in
/openrisc/trunk/or1ksim/configure
/openrisc/trunk/or1ksim/configure.ac
/openrisc/trunk/or1ksim/cpu/common/abstract.c
/openrisc/trunk/or1ksim/cpu/common/Makefile.in
/openrisc/trunk/or1ksim/cpu/common/parse.c
/openrisc/trunk/or1ksim/cpu/common/stats.c
/openrisc/trunk/or1ksim/cpu/dlx/Makefile.in
/openrisc/trunk/or1ksim/cpu/Makefile.in
/openrisc/trunk/or1ksim/cpu/or1k/Makefile.in
/openrisc/trunk/or1ksim/cpu/or1k/opcode/or32.h
/openrisc/trunk/or1ksim/cpu/or32/execute-fp.h
/openrisc/trunk/or1ksim/cpu/or32/execute.c
/openrisc/trunk/or1ksim/cpu/or32/generate.c
/openrisc/trunk/or1ksim/cpu/or32/Makefile.in
/openrisc/trunk/or1ksim/cpu/or32/or32.c
/openrisc/trunk/or1ksim/cuc/cuc.c
/openrisc/trunk/or1ksim/cuc/load.c
/openrisc/trunk/or1ksim/cuc/Makefile.in
/openrisc/trunk/or1ksim/debug/Makefile.in
/openrisc/trunk/or1ksim/doc/Makefile.in
/openrisc/trunk/or1ksim/doc/or1ksim.info
/openrisc/trunk/or1ksim/doc/version.texi
/openrisc/trunk/or1ksim/libtoplevel.c
/openrisc/trunk/or1ksim/Makefile.in
/openrisc/trunk/or1ksim/mmu/Makefile.in
/openrisc/trunk/or1ksim/or1ksim.h
/openrisc/trunk/or1ksim/peripheral/channels/Makefile.in
/openrisc/trunk/or1ksim/peripheral/Makefile.in
/openrisc/trunk/or1ksim/pic/Makefile.in
/openrisc/trunk/or1ksim/pm/Makefile.in
/openrisc/trunk/or1ksim/port/Makefile.in
/openrisc/trunk/or1ksim/support/dumpverilog.c
/openrisc/trunk/or1ksim/support/Makefile.in
/openrisc/trunk/or1ksim/testsuite/config/Makefile.in
/openrisc/trunk/or1ksim/testsuite/lib/Makefile.in
/openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in
/openrisc/trunk/or1ksim/testsuite/Makefile.in
/openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/spr-defs.h
/openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in
/openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in
/openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in
/openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in
/openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in
/openrisc/trunk/or1ksim/tick/Makefile.in
/openrisc/trunk/or1ksim/toplevel-support.c
/openrisc/trunk/or1ksim/vapi/Makefile.in

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.