URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [peripheral/] - Rev 483

Rev 483, 2011-02-01 09:18:23 GMT
Author: jeremybennett
Log message:
Updated with new opcodes to generate random numbers and to identify us as Or1ksim.

Path
/openrisc/trunk/or1ksim/ChangeLog
/openrisc/trunk/or1ksim/configure
/openrisc/trunk/or1ksim/configure.ac
/openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h
/openrisc/trunk/or1ksim/cpu/or32/insnset.c
/openrisc/trunk/or1ksim/doc/or1ksim.info
/openrisc/trunk/or1ksim/doc/or1ksim.texi
/openrisc/trunk/or1ksim/libtoplevel.c
/openrisc/trunk/or1ksim/NEWS
/openrisc/trunk/or1ksim/peripheral/memory.c
/openrisc/trunk/or1ksim/sim-config.c
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/spr-defs.h
/openrisc/trunk/or1ksim/toplevel-mprofile.c
/openrisc/trunk/or1ksim/toplevel-profile.c
/openrisc/trunk/or1ksim/toplevel-support.c
/openrisc/trunk/or1ksim/toplevel-support.h
/openrisc/trunk/or1ksim/toplevel.c