URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Last modification

• Rev 415, 2010-11-08 14:53:17 GMT
• Author: julius

• Log message:

  ORPSoC - ML501 update, working again.
  Documentation update including information on ML501 build
  OR1200 updates to do with instruction cache tag signal when
  invalidate instruction used.
  Added ability to define address to pass to SPI flash when
  booting.
  Added SPI sw test for board which allows inspection of
  data in a flash.

Path
/openrisc/trunk/orpsocv2/bench/verilog/eth_phy.v
/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile
/openrisc/trunk/orpsocv2/boards/README
/openrisc/trunk/orpsocv2/boards/tools.inc
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/bin
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/bin/xilinx_ddr2_if_cache.ngc
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/ml501.ucf
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/ml501_xst.ucf
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/prebuilt
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/run
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/run/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/ddr2_model_preload.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/orpsoc_testbench.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/par
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/orpsoc-defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/ml501.xcf
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/ml501_ddr2_wb_if_cache.ngc
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/ml501_xst.tpl
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/timescale.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/out
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/run
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/run/Makefile
/openrisc/trunk/orpsocv2/doc/orpsoc.texi
/openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_immu_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/sw/bootrom/bootrom.S
/openrisc/trunk/orpsocv2/sw/drivers/simple-spi/simple-spi.c
/openrisc/trunk/orpsocv2/sw/Makefile.inc
/openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c
/openrisc/trunk/orpsocv2/sw/tests/spi/board
/openrisc/trunk/orpsocv2/sw/tests/spi/board/Makefile
/openrisc/trunk/orpsocv2/sw/tests/spi/board/simplespi-readflash.c
/openrisc/trunk/orpsocv2/sw/utils/bin2hex.c